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What is between technology and ethics?
The ethical dilemma is created by the user’s addiction to computer hours, and much like any addiction it creates a type of alienation, through the media. We each build a world of “I” for ourselves through technology, while technology itself is incapable of touching our psyche, and a complex relationship is forged between human and media.
We become the creators of content, in which language and speech exist within this mythical space – a space where the dia-log and the multi-log become an a-log-arithm that produce this existentialism in which we live. We ask to create states of dialogs, where the medium takes active part.
Best Paper Award DVCon-Europe
Humanity is shifting the hegemony from science onto data. At Vtool, we continuously strive to reach a state where our minds do not explode from the excess of information particles that engulf us all, which the mind cannot contain. Vtool focuses on creating measuring perceptions that maintain the power of human consciousness.
DVCon China 2018
Visitors are an ideal way to externally and retroactively add functionality to UVM testbenches.
Reporting system using a dedicated tool such as Cogita, making the concept even better.
Particularly beneficial in large and complex SoCs, with large teams and many 3rd party IPs and VIPs .
Debug often takes a large portion of the chip development and can significantly disrupt schedules.
How can we make debug more predictable and faster?
Vtool’s Cogita provides “an approach that combines machine learning with advanced visualization, and an all-inclusive debug methodology, that has been proven to reduce the debug cycle dramatically”, said Hagai Arbel, Vtool CEO.
Read all about ‘Debug: The Schedule Killer’ in this Semiconductor Engineering article by Brian Bailey.
Is chip design and verification moving to the cloud?
Check out the Semiconductor Engineering video interview with Ann Mutschler and Hagai Arbel talking about the benefits of moving EDA tools to the cloud, as well as the main barriers causing a slow take-off for the semiconductor industry compared to other industries.
Find out what will drive this trend in the future and how Vtool’s Cogita is preparing for a seamless cloud integration in the link below.
Using Machine Learning in ASIC verification space depends on a number of factors, including sufficient high quality data.
“Verification data sources are almost inexhaustible,” says Darko Tomusilovic. “Data comes in many different forms including log files, waveforms, coverage data, and the code base itself.”
With Cogita, all this data can be merged in the same view and ML function applied to find the conclusions and dependencies from the input data, making the debug process faster and more efficient.
What skillset do engineers need for today’s ASIC verification?
“The best indicator of a good verification engineer is not the answers they give, but the questions they ask, and how quickly”, said Hagai Arbel, Vtool CEO. “Really brilliant verification engineers immediately grasp the uncertainty of what is not defined”.
It’s all about the engineering potential, and we at Vtool are proud to be nourishing engineers with an astonishing learning curve and teamwork mindset.
What exactly does “Done” mean when it comes to verifying a chip?
“Following the state-of-the-art definition of ‘done’ in verification does not guarantee that the design is bug-free. We need to formalize a way to log information and make conclusions, and not rely only on the experience”, said Hagai Arbel, Vtool CEO.
With Vtool’s Cogita, verification engineers are able to detect bugs that would have otherwise been missed. Cogita is transforming “done” to Done!
The ’20s brought on many changes for the chip industry: new markets, different architecture and virtual environment.
“Even though we all have a similar methodology, the semiconductor community needs to invest in standards for verification of the open-source, customizable CPU cores”, said Olivera Stojanovic, Project and Business Development Manager at #Vtool.
“Leveraging from faster communication and better ways to connect the team while working from home, gives companies competitive advantage”, said Darko Tomusilovic, Vtool Verification Leader.
In the remote work environment, Cogita verification teams can share information, results and conclusions and learn from one debug cycle to the next.
What does it take to be a great verification engineer? Is verification driven by a hunch that comes with experience or by logical thinking coupled up with discipline?
“After verifying numerous different chips, over time you develop a hunch where bugs can be found. However, what is needed is a good way to formalize the logging of the information and the ability to make conclusions, because you can only remember so much”, said Hagai Arbel, Vtool CEO.
To zero in on the bug elimination problem, we at Vtool developed Cogita that provides verification engineers with a clear, repeatable debug methodology, so that the whole verification team can benefit from the shared knowledge and power of Cogita’s AI.
Architectural tradeoffs vs. reuse and standards – how do you ensure your IC designs are forward and backward compatible, without carrying unnecessary complexities?
“Everything that goes into bigger systems has to be backward-compatible until all the old components in some system are replaced with the newer versions,” said Aleksandar Mijatovic, Digital Design Manager at Vtool, and Olivera Stojanovic, Project and Business Development Manager at Vtooll, adds, “Market demand and tradeoff between price (die size) and the volume dictate if the legacy features will be supported in the new versions of the chip.”
At Vtool we’ve been reinventing debug – with the power of AI, to cope with increasing complexity and more mission- and safety-critical SoC applications
“Instead of relying on our personal notebooks for our bug-finding activities, verification engineers can now turn to Cogita. It’s like an automated notebook and a debug companion reminding us if we’ve already done something or suggesting the best solution in similar situations,” says Darko Tomusilovic, Vtool Verification Leader.
The semiconductor industry is on a constant quest to speed up AI and ML, while optimizing hardware for vector instructions. This ultimately improves performance and power efficiency.
“Verifying vector instructions is done using the same workflow like any other processor verification, but the modelling of such instructions is much more complex,”explains
Darko Tomusilovic, Vtool Verification Leader.
⚡️ It’s efficiency we’re talking about, it’s all about efficiency ⚡️
Are your regressions optimally set to get results fast and reach coverage effectively?
Vtool’s experts Olivera Stojanovic and Darko Tomusilovic joined the conversation, sharing some tips and tricks on how to understand and utilize regression failure.
“Being one of the homelands for numerous tech innovations, Israel keeps bringing forth semiconductor startups by cultivating the entrepreneurial spirit and an excellent educational system,” says Hagai Arbel, Vtool CEO
Vtool proudly represents this innovative powerhouse community, in Israel and worldwide, and has always applied a long-term mindset focused towards consistent growth and impacting the future of technology.
In the article, Hagai Arbel discusses the ability of Israelis to create quality startups alongside their limited capacity to scale and morph into large, long-lasting semiconductors companies.
Let’s examine assertions… We all use them in formal verification, but what more can they be good for? Well, you have to be a pro to know, as Vtool’s expert Olivera Stojanovic says:
“Our verification experts find that the more assertions are used, the more value is gained. Assertions have been used in RTL design, formal and functional verification, shortening debug by identifying the buggy part of the code. The challenge for verification engineers is implementing and debugging complex assertions, used to check the protocol timings on the interface.”
Vtool is on a mission to enable faster, more effective verification
Darko Tomusilovic points out the importance of this, saying “There are plenty of times when real corner cases are not covered, simply because it was very difficult to express them using functional coverage language.”
Cogita’s visual diagnostics empowers debuggers to fully understand which combinations were hit, in any given simulation, avoiding coverage holes.
AI and humans – now, that’s a partnership we love to celebrate at Vtool. The challenge is always to efficiently leverage the strength of both.
Cogita is designed to help exactly where the human mind gets all boggled-up in the data, and cannot remember where they were in the verification process. “Cogita quickly and clearly presents the relevant data – visually, using ML/AI to help us see the bugs and debug much, much faster,”
said Hagai Arbel.
Time to market and the cost of SoCs are pushing companies to make decisions, which include open-source code and 3rd-party UVCs. This makes debugging very involved, you need to find the best way to handle huge logs while focusing only on the relevant ones. This issue goes to even higher dimensions if messages come from encrypted code, where you cannot fine-tune messages that will be visible.
“Including Cogita in the verification process for RISC-V based SoC projects helped our team with easy log handling and managing messages coming from different components,” says OliveraStojanovic, Vtool’s senior verification manager, in a this Semiengineering article.
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