Welcome to the New Verification Era of No Bug Escapes to Silicon

Debug Before Cogita

Verification before Cogita

Debug With Cogita

Verification with Cogita

Get your first-time-right ASIC with Cogita

One of the main problems in ASIC design is that the first-time-right rate is 30% and decreasing. Bugs find their way into silicon, even though 70% of frontend design is actually spent on verification. Defining 100% of code and functional coverage is problematic, as there is no guarantee that the design is bug free, regardless of verification time and effort.

Cogita helps you find ASIC logic bugs that would have otherwise been missed. It adds a layer of certainty that your chip will get its first silicon success.

Accelerate Debug with a Reliable and Clear Methodology

Although the majority of verification effort is spent on debug, there is no structured and  proven methodology on how to do it properly. Debugging is both hard to teach and hard to learn. Even when debugging is successful, it is difficult to repeat and reuse the conclusions in similar situations, due to our human tendency to forget. 

Cogita speeds up the debug process with a clear, repeatable methodology, enabling us to learn from one cycle to the next and share the debug knowledge across the team effectively.

Straighten the Last Mile Coverage Curve

The last 5% (“last mile”) of verification coverage is hard to predict and often requires as much as one third of the overall verification cycle time. This leads to failing to meet the deadline and ultimately going to tapeout with high risk. Thus, chip production start gets delayed. On top of that, the last mile of verification is not productive, as chances of finding a new RTL bug are low and the majority of effort is spent on debugging and fixing the testbench.

Cogita helps straighten this last-mile convergence curve and achieve 100% functionality on time.

How It Works

Cogita uses visualizion and ML algorithms to classify the data


Accelerated Verification Debug From Log to Visual

Cogita is a disruptive simulation debugging platform that harnesses the power of abstract visual structures, transforming verification debug processes into an effective ergonomic experience.

By leveraging next-generation advanced visualization technology, Machine Learning algorithms, and abstract data interpretation, it simplifies the heaviness of log files, streamlines the overflow of information, and unifies multiple multilayered data sources or types, to create impact through the eyes. Cogita means bug hunting at a glance.


Abstraction, for unified data.

Cogita aligns multiple sources into one comprehensive high-level view. Cogita can use any type of input, including UVM simulation log files, waveform databases, third-party VIP logs, embedded software logs, regression results, and any other type of data. No more switching around data formats. You get one coherent story, from one single source.


Visualization, for rapid inspection.

Cogita is built of visual structures, bringing back the most natural power people have for intuitive interpretation through sight. Textual input and numerical patterns are presented as colored bars across a timeline. This eliminates the typical debugging pattern of reaching a dead-end, then starting the process all over again. You don’t have to think or calculate. You clearly see it, understand it, and know what happened and where.


Machine-Learning Classification, for auto detection.

Cogita automatically spots anomalies in data structures, tests, packets, or transactions, using classification algorithms. Its ML algorithms prepare and screen any input data in massive amounts, and direct the next inspection point. You immediately grasp compound events, and move along the entire process.


Navigation, for space-time sync.

Cogita efficiently and dynamically navigates within the parallel dimensions of design space and time, concurrently. You easily follow the chain of cause-and-effect, each can answer each assumption clearly.

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