Vtool at DVCon US 2018 summary

Congratulations to our guys for their presentations at this year’s DVCon US:

 

Djuro Grubor – Verification Strategy for Pipeline Type of Design

Djuro showed how is it possible to create modular verification environment to correlate with design, incorporating an advanced UVM approach. As part of this presentation, it was shown how component synchronization and communication can be established using UVM TLM elements.

 

Darko Tomusilovic – UVM Verification Environment Based on Software Design Patterns

Darko had a presentation concerning software design patterns. Software design pattern is a technique utilized to tackle a commonly occurring problem in the software development. As a significant part of work done by verification engineers includes coding in an object-oriented language, such as SystemVerilog, many of the encountered challenges are suitable to be resolved applying certain design patterns. Their incorporation into the code provides many benefits, contributing to the code reusability and maintainability, and therefore improving the overall code quality.

 

Vtool DVCon US
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