Verification Convergence: Problem Definition

A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry.

While the doctor examined him I noticed that before tracing the problem itself, she asked some questions to rule-out a problem she was already familiar with and that can manifest itself in similar ways. Only then, after all the “okay, it is not that…good,” did she look at all aspects to conclude what the problem might be.

Why am I telling you all that? Because there is no fundamental difference between how this doctor did her diagnosis and our day-to-day bug hunting. Maybe we can learn something from her.

In my last blog, I discussed the long and tedious verification convergence phase. Every complex SoC leader knows how long and painful the process of converging verification effort toward the end of the project, and how hard it is to reach a low-enough risk for tapeout.

Read the entire blog post here in Semiconductor Engineering.

Vtool verification convergence
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