Have you ever found yourself in a pickle when trying to write some code and SystemVerilog keeps refusing to cooperate and doesn’t understand what you are trying to do? Yes… me too.
When you are just starting to learn, you are usually not aware of the little hacks that can make your life easier. So let me share one of those small tricks that can make your job less tedious, and more fun.
If you ever need to access some range of an array, which is variable, you cannot do it by writing for example:
array[i*8 : i*8 + 8]
SystemVerilog does not allow variables on the right hand side of the bit selection in the array.
Instead of this you can use:
array[i*8 +: 8]
This is called array slicing and you can read more about it here:
https://verificationguide.com/systemverilog/systemverilog-array-slice/
Example:
After executing:
