The new RISC-V SoC platform by Vtool and Codasip!

Vtool joined forces with the leading RISC-V vendor Codasip to deliver an even stronger Universa platform, powered by Codasip L31 CPU. This new integrated approach minimizes time-to-market dramatically, while also demonstrating the simple adaptability and extendability of Vtool Universa, especially now with Codasip’s core, support ecosystem, and documentation. In this blog post, we share why Vtool created the Universa HW/SW SoC solution, and how our partnership with Codasip is taking the platform to the next level.

The Vtool team wanted to find a new way to ensure fast time-to-market HW/SW development, by helping users kickstart their SoC quickly. It is clear that the industry is going in the direction of RISC-V, so we put our heads together to create and release our first flexible, configurable, and modular SoC solution, Universa. This platform is designed to be used as a hardware framework for evaluating customized peripherals, which is also applicable for ASIC software development and validation, advancing CPU-based ASIC platform development, facilitating CPU development, and more.
Vtool developed an initial SoC version, named Universa 1.0, which integrates AXI interconnect and the peripherals UART, I2C, and TIMER. We later upgraded it to include AHB interconnect, while changing the existing peripherals to be compatible with both AXI and AHB, and added two more peripherals, SPI and QSPI. Universa 2.0 was released with a set of peripherals that enable communication with external sensors, loading and executing software from external QSPI flash, evaluation of different HW/SW co-design optimization techniques, execution of Real-Time operating systems, and more.
Universa 1.0 and 2.0 had an open-source RISC-V single-core solution, allowing us to verify its features and perform HW/SW co-verification. After successfully verifying the overall solution, we tested Universa on an FPGA platform and developed Universa’s initial SDK package.

Now we felt it was time to take Universa up a notch. The platform was already compatible with any CPU, but we wanted to find a RISC-V-based CPU that proves Universa’s flexibility, in terms of hardware and software adaptations, and its broad applicability. We also wanted to verify the HW/SW solution performance and potential system bottlenecks using Vtool Cogita-PRO. So we set off to explore the RISC-V vendor market, seeking the best candidate that would ensure seamless integration and implementation by meeting our set of requirements, in both the hardware and software domains:

a) Data and instruction buses must be based on AXI or AHB protocols [HW requirement]
b) DMI interface support, to enable software debugging and faster software development [HW requirement]
c) Available startup procedures in the form of RISC-V assembly or C code, to run processors with minimal overhead [SW requirement)]
d) Quality documentation must be available from the core vendor, to understand the CPU’s ins and outs and for performing energy and performance software optimizations [HW/SW requirement]

After a long process of vetting various vendors, Codasip came on top. We reached out to them and opened discussions about a potential partnership, finding Codasip highly motivated to join forces and release a new Universa powered by Codasip core solution. From their wide range of RISC-V cores, they pointed us to several options that best fit our requirements alongside very detailed, well-structured documentation. The Vtool team chose Codasip L31 due to its high configurability, excellent real-time performance combined with various RTOS solutions, and low FPGA logic block footprint. The prospect of putting out a strong product together excited us all, we signed our mutual agreement within two weeks, and the integration process began immediately.

Since Vtool Universa and Codasip L31 core are both based on AHB buses, they integrate seamlessly. To enable software debugging and smooth software development, the L31 core DMI interface is connected to an FPGA boundary-scan JTAG interface through the JTAG2DMI IP block. The full solution was tested in simulation and on the FPGA platform. The Codasip OpenOCD script makes it easy to establish a debugging session, using a standard RISC-V GCC-based debugger.

Vtool_Codasip_Universa

Alongside Vtool’s modular hardware concept, Universa also targets modular software development as it comes complete with an SDK that integrates various software layers. To establish communication with internal peripherals, the SDK driver layer wraps driver libraries for all Universa peripherals. Since Universa peripherals are tested on different FPGA development boards, there are also various software libraries for communicating with the sensors. To demonstrate overall functionality, the SDK also includes software applications available under Bare-metal or FreeRTOS implementation.

Assisted by Codasip’s highly responsive support team, the complete integration process took no more than two weeks. On the hardware side, Vtool instantiated and connected the L31 using AHB interconnect and JTAG2DMI IP core, used for enabling debugging and software download procedures. From the software viewpoint, a minor Codasip startup procedure upgrade was required for integration purposes, enabling the Vtool Universa platform.

The Codasip L31 CPU, integrated with the Vtool Universa SoC platform, now forms the starting point for further optimizations to make the system more efficient. Codasip is the only company to enable easy processor customization by the user, leading to 10x to 100x efficiency improvements. This is called “Custom Compute” and requires much more than the right to modify the core! This capability is enabled by Codasip Studio automation: from a modifiable high-level description language called CodAL, the tools not only generate the hardware elements (including Verilog RTL) but also a full SDK that supports new custom instructions that users could create.

New efficiency and performance demands require users to optimize processors and systems. Vtool Universa powered by Codasip jump-starts and speeds up any full-scale SoC development process. The Codasip silicon-proven L31 RISC-V core is fully customizable with Codasip Studio at the microarchitecture and ISA levels, while Vtool Universa RTL design, verification environment, and SW are modular, adaptable, and extendable. It proves our integrated approach simplifies and optimizes your customization efforts while minimizing time to market.

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