Thank you Prof. Pavlidis for hosting us and giving us the opportunity to present the ASIC flow to young engineers!

Thank you Prof. Pavlidis for hosting us and giving us the opportunity to present the ASIC flow to young engineers! 🤘🏻

From conception to verification, we had a chance to share some valuable insights about the semiconductor ecosystem and our approach to digital design and verification!

It is always our pleasure to visit Aristotle University and exchange ideas that will bring you closer to the engineering field. 👨‍🚀

Looking forward to having us again!

Vtool_Greece_From_Conception_to_Verification_presentation

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