How to Continuously Monitor the Distance Between Two Signals Using a Macro
The precedence of operators in Systemverilog can sometimes be counterintuitive.
Operator precedence and potential problems
The precedence of operators in Systemverilog can sometimes be counterintuitive.
What can you do if you need to return two or more variables from a function?
SystemVerilog functions can have inputs and outputs. Using outputs is useful in case you want to return a queue from a function (or some other complex type), or in case you want to return two or more different variables from the function.
How do you do a memory model preload?
Have you ever tried to read bursts of data from any memory model before even writing any data? If so, you had to encounter “x” from all read addresses. Of course, this ”x” is not valid data to be read.