What can you do if you need to return two or more variables from a function?
SystemVerilog functions can have inputs and outputs. Using outputs is useful in case you want to return a queue from a function (or some other complex type), or in case you want to return two or more different variables from the function.
Join Vtool at Open Day in Nis!
Our Vtool community in Nis will be at the Open Day at the University of Nis, Faculty of Electronic Engineering!
How do you do a memory model preload?
Have you ever tried to read bursts of data from any memory model before even writing any data? If so, you had to encounter “x” from all read addresses. Of course, this ”x” is not valid data to be read.
Our Verification course in Nis has just began!
We are excited to open the 4th year of the Verification course at the Vtool lab in the University of Nis, Faculty of Electronic Engineering.
How to check if a file exists from a test?
Did you know that you can check inside your Specman code if a particular file exists in your project?
Next stop is JobFair in Nis!
Next stop is the Jobfair at Nis📍
Pass by our booth and grab the chance to meet our bug-fighters in person.
Vtool community is looking forward to meeting you.
How to use code refactoring in DVT?
This document shows how to use the Refactoring option in DVT in order to rename variables/classes/interfaces, and how to simply extract part of the code to a function.
Bidirectional assignment – tranif
If you are trying to model out a bidirectional mux, the tranif primitives might be more appropriate to use.
Array and queue randomization: foreach and unique constraint
Let’s say that you need to generate a random queue of data.
Did you know that you can run a command inside your Specman test?
Here are two ways to go about it: