How do we calculate the distance between two trigger points of one signal?
Our bug-fighters Aleksandra Dimanić & Nemanja Stevanović show us how to implement it with two different methods!
In cases when there are multiple UVCs of the same type, they will all use the same write function to pass their collected data items to the scoreboard or reference model.
Sometimes, there are cases when it’s required to start a single process multiple times in parallel, e.g. starting the same sequence on multiple sequencers of a given UVC.
Our Vtool community makes us so proud✨ Stefan Minić, Danijel Dimitrijevic, Vukasin Nikolic, Dušan Gocić, participated in the Humanitarian IT Race “Stafeta srcem”.
Olivera Stojanovic, our VP of Product, and Novak Radivojević, our verification engineer who also stints as a part-time academic assistant at the University of Niš, have joined Prof. Miona Andrejevic Stosovic to co-author a new and transformative textbook titled Functional Verification.
SystemVerilog functions can have inputs and outputs. Using outputs is useful in case you want to return a queue from a function (or some other complex type), or in case you want to return two or more different variables from the function.
Our Vtool community in Nis will be at the Open Day at the University of Nis, Faculty of Electronic Engineering!
Have you ever tried to read bursts of data from any memory model before even writing any data? If so, you had to encounter “x” from all read addresses. Of course, this ”x” is not valid data to be read.
We are excited to open the 4th year of the Verification course at the Vtool lab in the University of Nis, Faculty of Electronic Engineering.
Did you know that you can check inside your Specman code if a particular file exists in your project?