How do we calculate the distance between two trigger points of one signal?
How do we calculate the distance between two trigger points of one signal?
Our bug-fighters Aleksandra Dimanić & Nemanja Stevanović show us how to implement it with two different methods!
When using an array of UVCs, how can one tell which UVC sent an item to the scoreboard?
In cases when there are multiple UVCs of the same type, they will all use the same write function to pass their collected data items to the scoreboard or reference model.
How to start multiple instances of a single process in parallel using for/foreach loop?
Sometimes, there are cases when it’s required to start a single process multiple times in parallel, e.g. starting the same sequence on multiple sequencers of a given UVC.
Vtool Nis participated in the Humanitarian IT Race “Stafeta srcem”
Our Vtool community makes us so proud✨ Stefan Minić, Danijel Dimitrijevic, Vukasin Nikolic, Dušan Gocić, participated in the Humanitarian IT Race “Stafeta srcem”.
Functional Verification Book
Olivera Stojanovic, our VP of Product, and Novak Radivojević, our verification engineer who also stints as a part-time academic assistant at the University of Niš, have joined Prof. Miona Andrejevic Stosovic to co-author a new and transformative textbook titled Functional Verification.
What can you do if you need to return two or more variables from a function?
SystemVerilog functions can have inputs and outputs. Using outputs is useful in case you want to return a queue from a function (or some other complex type), or in case you want to return two or more different variables from the function.
Join Vtool at Open Day in Nis!
Our Vtool community in Nis will be at the Open Day at the University of Nis, Faculty of Electronic Engineering!
How do you do a memory model preload?
Have you ever tried to read bursts of data from any memory model before even writing any data? If so, you had to encounter “x” from all read addresses. Of course, this ”x” is not valid data to be read.
Our Verification course in Nis has just began!
We are excited to open the 4th year of the Verification course at the Vtool lab in the University of Nis, Faculty of Electronic Engineering.
How to check if a file exists from a test?
Did you know that you can check inside your Specman code if a particular file exists in your project?