Vtool goes to CadenceLIVE
Our bug-fighters will be at the Jobfair in Cacak, on 3rd of April, 10.00 – 16.00 CET!
Grab the chance to meet the team that creates added value to the society with cutting edge technology!
We are thankful for the opportunity to contribute to the University of Belgrade, School of Electrical Engineering.
Ljiljana Bjelicic met with Radivoje Djurić, the Head of the Department of Electronics, and Haris Turkmanovic, teaching assistant, to deliver five RISC-V trainer boards.
How to get a detailed description of an error in Cadence Xcelium tool
In this document it will be shown how to get a detailed description of the error in all stages of the simulation process when you run a test in Cadence Xcelium.
Compact GUI for executing your most often used commands
This document explains how to write a simple bash script for building a small GUI with different options to select a command which you may need frequently in your everyday work.
How to pass command line arguments in SystemVerilog?
In SystemVerilog you can pass arguments through the command line in order to avoid recompilation.