Strike to the right tone🎳

Strike to the right tone🎳
Our team in Poland gathered together in Krakow and Gliwice for an after – Easter celebration.

How to apply a stub on a selected instance of a given module

Vtool_Tips_Tricks_How_to_apply_a_stub_on_a_selected_instance_of_a_given_module

It is common, when working on a verification of a large design, that one wants to apply stub (or “blackbox”) only on a certain instance of a given module. This simply makes the simulation of this testcase much faster, and therefore accelerates the verification process.

The new RISC-V SoC platform by Vtool and Codasip!

Vtool_Universa_Codasip

Vtool joined forces with the leading RISC-V vendor Codasip to deliver an even stronger Universa platform, powered by Codasip L31 CPU. This new integrated approach minimizes time-to-market dramatically, while also demonstrating the simple adaptability and extendability of Vtool Universa, especially now with Codasip’s core, support ecosystem, and documentation.

AfterPATh, here we come!

Vtool_Greece_AfterPATh

Interested in learning how you can start your career in Verification or Digital Design? Join our bug-fighters Nikos Vogiatzis and Efstathios Faniadis, in Vtool presentation on April 6th, and elevate your career with us🚀

How to access out of scope signals when using SVA modules

Vtool_Tips_Tricks_Aleksandra_Zigan

Assertions are written inside SVA modules which are instantiated, using a bind statement, on top of most hierarchy levels that have all the signals needed for assertions. Sometimes, there is not one hierarchy that contains all of the necessary signals for a single assertion.

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