Recently, I had an interesting conversation with a verification leader of one of the world’s leading semiconductors companies. He has some 150 verification engineers in his organization and the group has been exploring EDA solutions for many years.
After Belgrade, Cacak, and Nis, our Novi sad team is growing rapidly, not to mention the wild opening party… Rule the bugs! Tel Aviv, Israel – April 14th, 2022 – After Belgrade, Cacak, and Nis, our Novi sad team is growing rapidly, not to mention the wild opening party… Rule the bugs! We at #Vtool […]
We are excited to announce our participation at ChipEx Israel on 10.05.2022! Tel Aviv, Israel – February 22th, 2022 – We will be there with the latest Cogita by Vtool and will be sponsoring the verification track.Step by our stand and hear our CEO Hagai Arbel speak about a new approach to ASIC Verification, Debugging […]
Today we will get into the sticky subject of bothersome fluctuation in field in registers.
Read here about a fairly simple method to attack this problem and make clean reusable code!
How many times did you have the task of creating a new UVC or testbench based on the old one?
Watch how Verification Engineer Tatjana Toroman lays out the way Cogita can cut through all of the irrelevant data found in large-sized logs, allowing us to see and work with only what we need!
Happy bug-hunting with Cogita!
We all know that large files can bog us down in debug, even using advanced editing tools, when using command lines is too slow and cumbersome.
Check out this video showing how Cogita can make handling large files and vast amounts of data easier and clearer, helping us hunt down bugs faster and more efficiently
Over the last 20 years, verification techniques have called for limited innovation compared to software, but for further evolution in the semiconductor industry, we need to continue finding better and more efficient debug methods.
While the fundamentals of good engineering remain the same, there’s always a better way to do ASIC verification, and this is exactly what our new Cogita machine learning features aim at – to develop new ways to accelerate debug and provide higher confidence for first silicon success.
Learn how to manipulate RTL signals from UVM classes in this Vtool Tips & Tricks article, using UVM HDL Backdoor Access support routines.
In this Tips & Tricks video and article, we explain the problem of setting multiple interface instances to their respective agents within your verification environment.