This document describes different approaches to debug constraint failures or subtle randomization mistakes from the command line.
During the verification process, It is very common to run many tests. In order to simulate each one of them you need to execute different test files separately. In case there is a significant amount of tests that have to be performed, this process can easily be extremely time-consuming.
All of us are using macro to define some values, etc, but do you know how to unleash the true form of macro?
How do we calculate the distance between two trigger points of one signal?
Our bug-fighters Aleksandra Dimanić & Nemanja Stevanović show us how to implement it with two different methods!
In cases when there are multiple UVCs of the same type, they will all use the same write function to pass their collected data items to the scoreboard or reference model.
Sometimes, there are cases when it’s required to start a single process multiple times in parallel, e.g. starting the same sequence on multiple sequencers of a given UVC.
When it comes to verifying a design block or a communication protocol, race conditions can cause a lot of issues.This can happen often due to the fact that an interface doesn’t have synchronization references.
If you are trying to access a memory from your UVM test, for example, to write a configuration for IP, or program for core, you perhaps want to use $readmemh. But how can we access memory from UVM?
SystemVerilog functions can have inputs and outputs. Using outputs is useful in case you want to return a queue from a function (or some other complex type), or in case you want to return two or more different variables from the function.
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