Recently, I had an interesting conversation with a verification leader of one of the world’s leading semiconductors companies. He has some 150 verification engineers in his organization and the group has been exploring EDA solutions for many years.
Over the last 20 years, verification techniques have called for limited innovation compared to software, but for further evolution in the semiconductor industry, we need to continue finding better and more efficient debug methods.
While the fundamentals of good engineering remain the same, there’s always a better way to do ASIC verification, and this is exactly what our new Cogita machine learning features aim at – to develop new ways to accelerate debug and provide higher confidence for first silicon success.
What is your sign-off criteria for verification? We all know that 100% of code and functional coverage is no guarantee that the design is bug free.
Check out Hagai’s latest blog discussing how Cogita’s visual analysis and classification algorithms provide another layer of certainty that we hit 100% coverage and have our ASIC first-time-right on silicon.