How do we enable delta events on waves in Xcelium?
If, for example, you have signals A and B that are supposed to be equal. You also have glitches in signal B. How do you avoid glitches in B?
If you have two signals that MUST be equal to one another all the time, and you need to write a checker for this, you can use the following..
If you ever need to do some Linux command straight from SystemVerilog or if you ever need to get an output of the command back to SV, you can use $system().
It’s possible to call UVM info from inside a property. This could be useful for logging the current status of an assertion for a property which consists of multiple steps.
This demonstration of the macro takes two signals as inputs and continuously calculates the delay in clock cycles between changes in those signals.
The precedence of operators in Systemverilog can sometimes be counterintuitive.
In order to turn off assertions for specific flow or configuration we can use $assertoff even though it will not stop or kill the assertions.
This document describes different approaches to debug constraint failures or subtle randomization mistakes from the command line.
During the verification process, It is very common to run many tests. In order to simulate each one of them you need to execute different test files separately. In case there is a significant amount of tests that have to be performed, this process can easily be extremely time-consuming.