How to check if a file exists from a test?
Did you know that you can check inside your Specman code if a particular file exists in your project?
We are thankful for the opportunity to contribute to the University of Belgrade, School of Electrical Engineering.
Ljiljana Bjelicic met with Radivoje Djurić, the Head of the Department of Electronics, and Haris Turkmanovic, teaching assistant, to deliver five RISC-V trainer boards.
How to use code refactoring in DVT?
This document shows how to use the Refactoring option in DVT in order to rename variables/classes/interfaces, and how to simply extract part of the code to a function.
How to get a detailed description of an error in Cadence Xcelium tool
In this document it will be shown how to get a detailed description of the error in all stages of the simulation process when you run a test in Cadence Xcelium.
Bidirectional assignment – tranif
If you are trying to model out a bidirectional mux, the tranif primitives might be more appropriate to use.
Compact GUI for executing your most often used commands
This document explains how to write a simple bash script for building a small GUI with different options to select a command which you may need frequently in your everyday work.
Array and queue randomization: foreach and unique constraint
Let’s say that you need to generate a random queue of data.
Did you know that you can run a command inside your Specman test?
Here are two ways to go about it:
How quickly does it take to check if an element is part of an array?
How quickly it takes to check if an element is part of an array.
How to pass command line arguments in SystemVerilog?
In SystemVerilog you can pass arguments through the command line in order to avoid recompilation.