Chip Verification – The Future of Technology
On Thursday March 16th at 4:20PM, our CEO Hagai Arbel will talk about the process of designing new chips and the challenges of making them work.
Our Verification course in Nis has just began!
We are excited to open the 4th year of the Verification course at the Vtool lab in the University of Nis, Faculty of Electronic Engineering.
Next stop is JobFair in Nis!
Next stop is the Jobfair at Nis📍
Pass by our booth and grab the chance to meet our bug-fighters in person.
Vtool community is looking forward to meeting you.
Vtool is excited to announce the release of Universa, our integrated HW/SW ready-to-use RISC-V SoC.
Universa provides a modular, easily adaptable and extendable RTL design, UVM/SV verification environment, and ready-to-go drivers and SW examples.
Vtool Cogita-PRO
Vtool Cogita-PRO is an AI-based verification analytics and debugging solution.
Developed by engineers for engineers, Cogita-PRO is the next leap in resolving the ever-increasing need for ASIC verification closure on-time and first-time-right.
DVCon U.S. 2023 is just around the corner!
It’s that time of the year again!
DVCon U.S. 2023 is just around the corner, San Jose, CA, Feb 27 – Mar 2. We’ll be in booth 123.
Looking forward to seeing you all there.
We are thankful for the opportunity to contribute to the University of Belgrade, School of Electrical Engineering.
Ljiljana Bjelicic met with Radivoje Djurić, the Head of the Department of Electronics, and Haris Turkmanovic, teaching assistant, to deliver five RISC-V trainer boards.
Vtool is proud to join RISC-V International as a strategic member.
As a multidisciplinary team of experts in ASIC design, verification, and embedded software, Vtool is well positioned to design top-notch RISC-V-based systems.
Did you know that you can run a command inside your Specman test?
Here are two ways to go about it:
How quickly does it take to check if an element is part of an array?
How quickly it takes to check if an element is part of an array.