Over the last 20 years, verification techniques have called for limited innovation compared to software, but for further evolution in the semiconductor industry, we need to continue finding better and more efficient debug methods.
While the fundamentals of good engineering remain the same, there’s always a better way to do ASIC verification, and this is exactly what our new Cogita machine learning features aim at – to develop new ways to accelerate debug and provide higher confidence for first silicon success.
In this Tips & Tricks video and article, we explain the problem of setting multiple interface instances to their respective agents within your verification environment.
So what makes debugging such a complicated process consuming ~50% of the hardware verification development cycle?
First of all, it is a process too prone to losing data. Any previous debugging cycle barely helps the following. Apart from our notebooks and memories, we do not have a practical way to collect debugging steps and rely on them to resolve similar problems.
What is your sign-off criteria for verification? We all know that 100% of code and functional coverage is no guarantee that the design is bug free.
Check out Hagai’s latest blog discussing how Cogita’s visual analysis and classification algorithms provide another layer of certainty that we hit 100% coverage and have our ASIC first-time-right on silicon.
Breaking down the debug process into 6 simple steps, how can we further simplify the complex bug hunting? The debug steps can be centralized in a single interactive platform, easily navigated and optimized with Cogita. Find out all the details of debug optimization in this blog
How many times did you hear yourself or a verification teammate say “I’m almost done”, while 100% coverage was many weeks away?
Hagai Arbel explains how Cogita can help converge on the last 10%, faster and smoother ?.
Can you find the hidden pattern without the color or shape?
Visualization is power. Your eyes pin down patterns, quicker than your mind reads text. It’s instinct.
What about when you deal with complex failing simulation scenarios? Is this also a moment for letting your ‘visual processors’ take control and lead the way?
We invite you to read a short story of how Cogita was born, on Vtool’s journey to leverage people’s inherent visual power for hunting down bugs – following their eyes.
Methodology or problem-solving. Should you follow a proven verification path or blaze your own way forward?
“When I was 18, I bought a Vespa ’67: the famous Italian scooter… One day, I began to hear strange voices from inside the engine. This kicked off several weeks of nighttime debugging. It was my first real engineering job,” recounts Vtool CEO, Hagai Arbel, in his new post on our blog #RuleTheBugs, sharing his angle on the tradeoffs of following a proven methodology step-by-step instead of exploring your own path of discovery.
Scooters or chips, our passion is to simply achieve a #BugFreeWorld?
We are happy to announce an exciting new feature called Log Analyzer. The Log Analyzer quickly finds bugs by pinpointing where and when failures occur. It displays only what you are looking for at a given moment.