Who Will Own Debug?

Vtool Verification

Recently, I had an interesting conversation with a verification leader of one of the world’s leading semiconductors companies. He has some 150 verification engineers in his organization and the group has been exploring EDA solutions for many years.

We are excited to announce our participation at ChipEx Israel on 10.05.2022!

We are excited to announce our participation at ChipEx Israel on 10.05.2022! Tel Aviv, Israel – February 22th, 2022 – We will be there with the latest Cogita by Vtool and will be sponsoring the verification track.Step by our stand and hear our CEO Hagai Arbel speak about a new approach to ASIC Verification, Debugging […]

Easy Log Manipulation

How to get your team to the next level

Watch how Verification Engineer Tatjana Toroman lays out the way Cogita can cut through all of the irrelevant data found in large-sized logs, allowing us to see and work with only what we need!

Happy bug-hunting with Cogita!

Quickly navigate through your log

How to get your team to the next level

We all know that large files can bog us down in debug, even using advanced editing tools, when using command lines is too slow and cumbersome.

Check out this video showing how Cogita can make handling large files and vast amounts of data easier and clearer, helping us hunt down bugs faster and more efficiently

Visual Debug Platform – Cogita New Release

Debug with Cogita

Vtool announced today the latest release of its Cogita, visual debug platform. Cogita is used in ASIC verification to accelerate debug and help achieve faster chip development cycles with much higher confidence of first-time-right silicon.

The latest Cogita version 3.8.0 includes features that allow faster debug capabilities.

Invent A New Way To Do Your Job

Cogita - debug innovation

Over the last 20 years, verification techniques have called for limited innovation compared to software, but for further evolution in the semiconductor industry, we need to continue finding better and more efficient debug methods.

While the fundamentals of good engineering remain the same, there’s always a better way to do ASIC verification, and this is exactly what our new Cogita machine learning features aim at – to develop new ways to accelerate debug and provide higher confidence for first silicon success.

Bug Escapes And The Definition Of Done

Bug escapes - bugs per week

What is your sign-off criteria for verification? We all know that 100% of code and functional coverage is no guarantee that the design is bug free.

Check out Hagai’s latest blog discussing how Cogita’s visual analysis and classification algorithms provide another layer of certainty that we hit 100% coverage and have our ASIC first-time-right on silicon.

Six Steps of Bug Hunting

Debugging with Cogita

Breaking down the debug process into 6 simple steps, how can we further simplify the complex bug hunting? The debug steps can be centralized in a single interactive platform, easily navigated and optimized with Cogita. Find out all the details of debug optimization in this blog