Our Vtool community makes us so proud✨ Stefan Minić, Danijel Dimitrijevic, Vukasin Nikolic, Dušan Gocić, participated in the Humanitarian IT Race “Stafeta srcem”.
When it comes to verifying a design block or a communication protocol, race conditions can cause a lot of issues.This can happen often due to the fact that an interface doesn’t have synchronization references.
Olivera Stojanovic, our VP of Product, and Novak Radivojević, our verification engineer who also stints as a part-time academic assistant at the University of Niš, have joined Prof. Miona Andrejevic Stosovic to co-author a new and transformative textbook titled Functional Verification.
Our experienced bug – hunter Adam Gołda, will present results of research and development on nanometer MOSFET modeling in Krakow, 29th – 30th of June.
The new Vtool-Incusolution partnership will bring Vtool’s diversified offering to leading chipmakers in Korea, offering Vtool’s advanced verification and debugging tool Cogita-PRO, its RISC-V-based SoC framework Universa, and top-notch ASIC HW/SW services.
Our bug-figthers Joel Samuel, Raghavendra Moorthi, Roopa M and Shejal Singh will attend the Spacetronics and Deftronics Summit at Hilton Bengaluru Embassy Manyata Business Park in India🚀
If you are trying to access a memory from your UVM test, for example, to write a configuration for IP, or program for core, you perhaps want to use $readmemh. But how can we access memory from UVM?
SystemVerilog functions can have inputs and outputs. Using outputs is useful in case you want to return a queue from a function (or some other complex type), or in case you want to return two or more different variables from the function.
obFair Xanthi, here we come🚀
Join our bug-fighters in Xanthi, pass by our booth and accelerate your career at Vtool🐞
Come see how Vtool supports your success with our new Universa RISC-V SoC, Vtool’s Cogita-PRO EDA solution, and our AtoZ HW/SW consulting services.