In the 1990s, the National Semiconductor Israeli site in Herzliya was responsible for the design and verification of the company’s flagship RISC processor.
That was the place and the time when the concept of constraint-random, abstract, coverage-driven verification was born. Engineers realized that without a random generation of stimuli opcodes, it would be very hard to fully verify new processors. Later on, some of these CAD and verification engineers started Verisity and the rest is history.
I did not know it back then but joining this team, fresh from faculty, affected my professional life in many ways. One of my first tasks as a junior verification engineer was to verify a block written by A, a senior designer who was known as someone who has no bugs.
I was told again and again, in the corridor or around the coffee machine, that everyone else was creating bugs. But not A. The guy was a super designer. He had no bugs.