How to verify the duration of any signal using SVA?

Very often, there is a need to check if a signal was asserted/stable for a number of clock cycles. If the number of cycles is fixed, this can easily be checked with an assertion using a consecutive repetition operator. Let’s say there is a signal x which has to be asserted for exactly 10 cycles (deasserted after) when a trigger signal start is asserted as well.

Vtool_How_to_verify_the_duration_of_any_signal_using_SVA

In case the number of cycles has to be parametrized, this approach won’t work because the consecutive repetition operator can only take constants and not variables. Here’s an example of how parametrization can be achieved using local variables and property arguments:

Vtool_How_to_verify_the_duration_of_any_signal_using_SVA_

Properties can take arguments in a way that is similar to functions and tasks. Here, we pass len as the number of cycles instead of hard-coding it to 10. We can also declare local variables inside properties, which can later be modified, updated and used in checking. In this case, we use a local variable cnt to count the cycles.

When start is asserted, cnt is set to 0. From the next cycle on, x is repetitively checked (using [*]) while cnt is increased. Once cnt reaches len, we check if x is deasserted.

Note: Using [*] can cause a performance drop in case len is a big number or many signals need to be checked this way.

If you do not have a start signal, and you want to check only x itself, you can use the following:

Vtool_How_to_verify_the_duration_of_any_signal_using_SVA_

The cnt < len ensures that the x is not stuck on high.

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