How to use “bind” to connect interfaces to modules in System Verilog?

SystemVerilog provides a “bind” construct that is used to specify one or more instantiations of a module, interface, or checker without modifying the code of the target.

Let’s say that there is some block which you need to monitor. There are 10 instances of that block, and you need to access each one. You would have to connect 10 instances of an interface to those 10 blocks from the design. This can be tedious work and prone to errors. This is where bind comes in handy.

Bind can be used to connect a specific interface to a specific module, to connect another module with assertions or coverage to design, etc.

Take a look at this EDA playground example to see how bind can be used to automatically connect to all instances of a specific module.

If you open waves you can see the difference between binding to all instances, or to a specific instance. On the left, each module gets its own version of the interface and assertion module. On the right only a specific module gets them.


Bind syntax:



One more useful thing you can do if you want to make accessing each interface easier is to add another layer to the binding.

You can create a wrapper interface which will help with setting that specific interface to config db.

You also have to bind that wrapper interface to dut instead.



Take a look at this other EDA playground example to learn more about this.

After running the simulation, notice that we now have a queue of interfaces, where each interface is set to config db under a different name:


You can also manipulate these strings to set a prettier or more convenient name to config db, but that is project-specific and depends on your needs. This is just a general idea of how it can be used.

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