In SystemVerilog you can pass arguments through the command line in order to avoid recompilation.
Two types of arguments:
- $test$plusargs(<string>)
- $value$plusargs(<string>, <value>)
You can use the first one if, for example, you want to avoid creating two different tests for similar scenarios.
Example 1:
You can use the second one if you need to pass specific values through the command line.
Example 2:
If you want to change verbosity from command line, you can set up your environment like this:
Both of these are controlled from command line by expanding run command with:
+EXTRA_ARG
+VERBOSITY=UVM_HIGH
Read more about this here:
https://www.chipverify.com/systemverilog/systemverilog-command-line-input