When it comes to verifying a design block or a communication protocol, race conditions can cause a lot of issues.This can happen often due to the fact that an interface doesn’t have synchronization references.
A simple way to deal with it is by delaying the assignment of the responsible signals. This can lead to more issues regarding the handling of the signals or the general implementation of the protocol specs.
This is where Clocking Blocks come to solve these problems. Clocking blocks are used inside an interface or a module. Their purpose is to define the sampling time of the inputs and the driving time of the outputs. Generally, clocking blocks handle given signals that are synchronous according to a specific clocking event. This can make the timing more explicit while solving any racing issues.
The default skew for inputs is #1step before the event while for outputs is #0ns after the event occurs. This can change by setting different default input/output timing skews or by declaring a separate skew for each input/output. Moreover, it is important to be noted that the skews are based on the timescale of the project, while they can be based on clocking cycles by using “##”.
