How to Fix the Issue with “Generate” Loop Label?

This article shows how to recognize compilation issues with unlabeled “generate” loops in the design.

 

If you are trying to access a module somewhere inside of the DUT hierarchy, you may encounter an issue on the way to the module if it is instantiated by a generate loop that is not explicitly labeled with a name, which will in that case be labeled implicitly during elaboration.

 

If that is the case, you will get this error in Cadence Xcelium:

 

xmelab: *E,CUVIMG (<file_where_module_is_located>): Implicit name not allowed in hierarchical name.

 

In case this happens to you, and you absolutely need to access this module via the HDL path, kindly ask your designer to explicitly label the “generate” loop.

 


 

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