All of us are using macro to define some values, etc, but do you know how to unleash the true form of macro?
Here is an example replace function new from the uvm by macro:
Instead of creating new objects with boring formulas we can also use macro:
Now some theory on how to use macro:
1. Single line macro:
2. Multiline macro:
Example:
Macro will looks like this:
3. Macro with ““”
Example:
Macro will looks like this:
4. Macro with “`””:
Example:
Macro will looks like this:
5. Macro with escape backslash “`\`””:
Example:
Macro will looks like this:
And that is all! Now you can be friends with SystemVerilog macro!