How to apply a stub on a selected instance of a given module

It is common, when working on a verification of a large design, that one wants to apply stub (or “blackbox”) only on a certain instance of a given module. This simply makes the simulation of this testcase much faster, and therefore accelerates the verification process.

What is a stub / blackbox ?

In short, it is a hollow version of a given module. In other words, the interface (inputs outputs, parameters) of this module remains the same, but its interior part is empty. Blackboxed module just lacks all its functionalities, except for issuing appropriate output signals (like “ready”) so that the higher level pipeline does not get stalled.


What is a logical library ?
Understanding the concept of a logical library is crucial to understanding the following information.

A logical library is a compilation database of a simulator. It works similarly to libraries in C/C++. In the elaboration step, a compilation/elaboration tool merges all the logical libraries in order to create an executable binary file. Usually, in verification, the default logical library is called “work”, however, more sophisticated verification environments store some pieces of code in specific logical libraries. For example, all testbench related file go to LIBVERIF library, and all RTL related files go to LIBRTL library.

What does stubs application flow usually look like ?
The most straightforward, and most common way for applying stubs is preparing a hollow version of a module of interest, and replacing the original module in the compilation filelist with the hollow one.
Although this solution is simple and in most cases works as expected, it has one significant drawback – a stub gets applied to all instances of a given module within the design.
Hence, sometimes the question arises ….

How to apply a stub only to a selected instance of a given module ?
The solution for this is to use the System Verilog Configuration block. The configuration block is used by the simulator at the elaboration stage. As one logical library might contain only one module of a given name, we have to compile original modules and hollow versions of these modules to separate logical libraries. Then, in the SV configuration block, we explicitly indicate which logical library should be considered as a source of implementation for a given instance of a module.

To understand how it works, let’s consider an example of a design which implements two instances of a module “flp_multiplier” and two instances of a module “flp_adder”. The hierarchical paths to these instances, starting from the top testbench file, are as follows:


Then, let’s assume that you want to apply stubs on the first instance of “flp_multiplier” and on the second instance of “flp_adder”, preserving other instances intact.
The steps to do so are as follows:

  1. Create hollow versions of “flp_multiplier” and “flp_adder” modules, keeping in mind that its names and its interface signals have to remain the same as in the case of original modules that you want to substitute.
  2. Decide the names of logical libraries you want to use. Here, we assume that all TB related files will be compiled to a library called LIBVERIF, RTL related files will be compiled to a library called LIBRTL, and stubs will be compiled to a library called LIBSTUBS. In case we use VCS, we have to prepare a “synopsys_sim.setup” file so that VCS is aware of all the logical libraries we want to use. In our case it could look like this:

3. Prepare SV configuration file. At this step, we indicate which instances of given modules we want to suppress with stubs, and from which logical libraries these stubs should be taken:


4. Include SV configuration block in testbench filelist, (e.g. tb_filelist.fl), and compile all logical libraries. Here, stubs are listed in “stubs_filelist.fl”.


5. Run elaboration. At this stage remember to specifically indicate to the tool to take your SV configuration block into account. In case of VCS you can do it by passing the name of the configuration block to elaboration tool:


That’s basically it. Although this example uses VCS, the same approach should work similarly with any other tool.

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