Cogita Challenge

Find the failure root cause in your RTL and testbenches and understand the scenario of log files in less than 2 hours.

Uncover the new, faster and more efficient Cogita debug!

Is The Cogita Challenge for you?

Do you have failing tests, and you’ve spent too much time finding the root cause without success?
Do you have regression errors, and you want to spot performance bottlenecks?
Would you like to compare similar passing and failing tests to explore the root cause?
Do you have problems in pinpointing the issues in the testbench?

If your answer is yes to any of these questions – congratulations! You have qualified for the Cogita Challenge! Let Vtool’s Cogita help you find the issues by visual representation of the log file data. Cogita’s ML can provide conclusions and dependencies from the input data.

What is the input for the Cogita Challenge?

Send us one or more log files (either passing or failing, or both). The log files can be from different sources – eg. Simulation log, Tarmac, etc, and we can perform a merged evaluation on all the information provided from all the log sources in a single Cogita view.

Your log file should have:

Enabled full verbosity
Massive traffic.

In addition to the log files, you can optionally also provide an image of high-level verification environment topology.

What do you get from the Cogita Challenge?

When you send us the log files, we will analyze them internally with Cogita and present the results to you over a two-hour joint session. We will show how your debug process can be accelerated, and provide a more efficient way to understand the random scenarios using Cogita.

You will also learn how you can save Cogita configurations for reuse on derivative designs. Finally, with Cogita you will get a report with a list of issues and conclusion for your log file.