Verification engineers often see a test that passed before now fails. The main question is what has changed? The best way to figure this out would be to compare two log files and try to notice the difference.
But sometimes spotting the differences, finding what went wrong in a failed test, can take hours of work.
This white paper looks at Cogita’s unique compare function, that allows engineers to see the differences immediately and find the cause of the failure faster. As a visualization tool, Cogita processes massive amounts of data and provides a much clearer and intuitive way for debugging and analysis.
Download the white paper here to see how Cogita helps you see and manage only the data you need to.
Company-X develops complex ASICs and FPGA that facilitate massive traffic from CPUs to memory.
Company-X verification team inferred from previous projects that such a subsystem verification will take 10 months for 4 engineers.
We explain the main functionality of the DUT and testbench and the challenges in debugging that Cogita, later on, was able to solve.
In every complex SoC verification process, it is necessary to activate the CPUs during verification and to check the operation of the software they execute alongside the test’s scenarios. At a minimum, basic scenarios such as “boot rom execution” are tested, but in many cases, further scenarios are required. The CPUs themselves are usually proven IPs, but in order to verify their integration and operation within the SoC, it is not enough to connect a VIP to the CPU bus and have it imitate the CPU’s behavior.
While semiconductor verification techniques have evolved considerably over the last 25 years, the debug of design problems found during verification has barely changed. New algorithms including machine learning, visualization approaches, and problem solving ideas allow a different approach to debug that saves up to an order of magnitude in debug time.