Accessing a memory via the backdoor in a UVM testbench
If you are trying to access a memory from your UVM test, for example, to write a configuration for IP, or program for core, you perhaps want to use $readmemh. But how can we access memory from UVM?
What can you do if you need to return two or more variables from a function?
SystemVerilog functions can have inputs and outputs. Using outputs is useful in case you want to return a queue from a function (or some other complex type), or in case you want to return two or more different variables from the function.
How do you do a memory model preload?
Have you ever tried to read bursts of data from any memory model before even writing any data? If so, you had to encounter “x” from all read addresses. Of course, this ”x” is not valid data to be read.
How to check if a file exists from a test?
Did you know that you can check inside your Specman code if a particular file exists in your project?
How to use code refactoring in DVT?
This document shows how to use the Refactoring option in DVT in order to rename variables/classes/interfaces, and how to simply extract part of the code to a function.
How to get a detailed description of an error in Cadence Xcelium tool
In this document it will be shown how to get a detailed description of the error in all stages of the simulation process when you run a test in Cadence Xcelium.
Bidirectional assignment – tranif
If you are trying to model out a bidirectional mux, the tranif primitives might be more appropriate to use.
Compact GUI for executing your most often used commands
This document explains how to write a simple bash script for building a small GUI with different options to select a command which you may need frequently in your everyday work.
Array and queue randomization: foreach and unique constraint
Let’s say that you need to generate a random queue of data.
Did you know that you can run a command inside your Specman test?
Here are two ways to go about it: