How to start your first embedded project
In this video, find out how to start your first embedded project. You will learn how to generate C code for a specific microcontroller and how to toggle LED diode.
How to manipulate RTL signals from UVM classes
Learn how to manipulate RTL signals from UVM classes in this Vtool Tips & Tricks article, using UVM HDL Backdoor Access support routines.
Multiple Interface Instances
In this Tips & Tricks video and article, we explain the problem of setting multiple interface instances to their respective agents within your verification environment.
Extension Object
Extension object is a technique which allows us to generate customized register bus access transactions using UVM register model.
Verilog Generate: Variable vs Signal Value
In this video we talk about a common generate block evaluation issue. We compare signal with generate variable. Find out why the design won’t compile and how to overcome this problem.
UVM reg field abstraction
Find out the difference between the mirrored value, the desired value and the value of UVM reg field