National Semiconductor’s design center (NSTA) in Herzliya was the place where I fell in love with chip verification. I joined the team in 1999, still during my BSc, and met a group of innovators with a passion to create great ASICs and improve the way we did it at all costs.
It was fast-moving learning for me, both on the verification engineering and verification management sides of things. Most of my managerial skills I learned from Limor who is a dear friend of mine still today.
One day, I saw for the first time the famous metric of the Bugs-Per-Week chart (BPW). BPW collects the bugs found every week by the verification team in order to help determine the chip’s readiness for tapeout.
Managers expect the trend will show more and more bugs as the team is getting to speed, then less and less as the design gets cleaner. Different companies are using different thresholds of the chart as a checklist item for tapeout.
You know how sometimes something looks off to you from a first glance? But everyone around treats it as a trivial fact and then with time it makes sense to you as well? And every once in a while you ask yourself: Does this really make sense?
Well, I remember myself saying to Limor, “You know, what we really should be counting is the bugs left in the design, not the ones we already found. What if the declining trend of BPW is because the verification team simply got tired and had a hard time finding these stubborn bugs?”