It’s possible to call UVM info from inside a property. This could be useful for logging the current status of an assertion for a property which consists of multiple steps.
The precedence of operators in Systemverilog can sometimes be counterintuitive.
This document describes different approaches to debug constraint failures or subtle randomization mistakes from the command line.
In cases when there are multiple UVCs of the same type, they will all use the same write function to pass their collected data items to the scoreboard or reference model.
Sometimes, there are cases when it’s required to start a single process multiple times in parallel, e.g. starting the same sequence on multiple sequencers of a given UVC.