How to become friends with SystemVerilog macros?
All of us are using macro to define some values, etc, but do you know how to unleash the true form of macro?
Accessing a memory via the backdoor in a UVM testbench
If you are trying to access a memory from your UVM test, for example, to write a configuration for IP, or program for core, you perhaps want to use $readmemh. But how can we access memory from UVM?