If, for example, you have signals A and B that are supposed to be equal. You also have glitches in signal B. How do you avoid glitches in B?
If you have two signals that MUST be equal to one another all the time, and you need to write a checker for this, you can use the following..
If you ever need to do some Linux command straight from SystemVerilog or if you ever need to get an output of the command back to SV, you can use $system().
This demonstration of the macro takes two signals as inputs and continuously calculates the delay in clock cycles between changes in those signals.
How do we calculate the distance between two trigger points of one signal?
Our bug-fighters Aleksandra Dimanić & Nemanja Stevanović show us how to implement it with two different methods!
Sometimes, there are cases when it’s required to start a single process multiple times in parallel, e.g. starting the same sequence on multiple sequencers of a given UVC.
SystemVerilog functions can have inputs and outputs. Using outputs is useful in case you want to return a queue from a function (or some other complex type), or in case you want to return two or more different variables from the function.
This document shows how to use the Refactoring option in DVT in order to rename variables/classes/interfaces, and how to simply extract part of the code to a function.
Let’s say that you need to generate a random queue of data.
How quickly it takes to check if an element is part of an array.