Accessing a memory via the backdoor in a UVM testbench

If you are trying to access a memory from your UVM test, for example, to write a configuration for IP, or program for core, you perhaps want to use $readmemh. But how can we access memory from UVM? Here is a basic example of how to do it:

1.Create abstract class with functions for write, read etc:

2.Create normal class, this class will be extending our abstract class and add define with her path to memory

3.Create object of this class in top_tb and put this to config_db

4.Then get this object in base_test:

5.And that is all, now you have access by backdoor to memory in our testbench
Example on EDA:
https://www.edaplayground.com/x/Rfjn

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